SRAM memory arrays use more n-channel (NMOS) field effect transistors (FETs) than conventional dynamic random access memory (DRAM) arrays and are thus capable of storing data without the need to constantly refresh the memory cells as is required in DRAM technology. However, the cross-coupled nature of the SRAM cell allows manufacturing defects to exist within the cell and not necessarily cause the cell to improperly function within the normal operating range when it is first tested, but which may cause it to fail later.
Semiconductor devices in general are commonly subjected to a series of test procedures in order to assure product quality and reliability. Product reliability is a product's ability to function over time within given performance limits under specified operational conditions. These testing procedures conventionally include probe testing, in which an individual die, while still on a wafer, is initially tested to determine functionality and possibly speed. If the wafer has a yield of functional dice which indicates that the quality of the functional dice is likely to be good, each individual die is assembled in a package. Conventionally, the packaging includes mounting the die on a lead frame and encapsulating it in a plastic housing with external leads for electrical connection purposes.
The packaged devices are then subjected to another series of accelerated life testing, which includes burn-in and discrete functional testing. Burn-in detects and weeds out infant mortality failures by exercising the devices and subjecting them to temperature and voltage stresses. Infant mortality refers to those devices that would fail early in their lives due to manufacturing defects. Burn-in accelerates device failure by electrically exercising the devices at elevated temperatures in a burn-in oven adapted for that purpose. Functional testing permits the devices to be tested for speed and for errors which may occur after assembly and after burn-in.
Functional tests can include low and high Vcc margin and bump retention tests. In a bump retention test, for example, voltage is dropped down to a predetermined low level during a read to detect whether the memory device will read correctly or whether it will unacceptably change its memory state. The ability of a cell to retain its data (and not change states) when being read is known as its static noise margin (SNM). Defective cells have a lower SNM than good cells. In other words, the more SNM the cell has, the less likely it is to change states during a read.
Although normal acceptable working voltage levels for a five (5) volt SRAM device may be in the range of 4.5 to 5.5 volts, a bump retention test may drop the voltage down to as low as 2.2 volts to test the extreme functional limits of the device. If the device retains its data and reads properly during the low voltage test state, it is deemed a function device. On the other hand, if a memory cell (or cells) in the device unacceptably changes states, the device fails the test and is discarded.
Alternatively, instead of using a predetermined low voltage, a more complete voltage search test may be performed wherein various low voltage levels are applied incrementally to determine what the functional voltage limits of the array of cells are. This test is often used to determine a point of full array failure, meaning the voltage level at which most, if not all, of the cells unacceptably change states. However, this test is time consuming and costly and so is performed only when deemed cost effective.
Bump retention tests can be performed either at wafer sort or in packaged part testing. Although this type of testing screens out most defective SRAM cells, it retains certain inherent limitations. For example, it is known that some defective cells are not detected during a low voltage bump retention read test due to, possibly, the reaction of peripheral circuitry characteristics in the SRAM device during the low voltage portion of the test. Essentially, when extreme low or high voltages are applied to an SRAM device for specific test purposes, all circuitry in the device is subject to the same test voltage level without any isolating effects for peripheral circuitry. The problem associated with all circuitry being subject to the same test voltage level is that certain peripheral circuitry (for example, wordlines) should selectively retain a normal acceptable voltage level (different from the test voltage level) for improved testing conditions and to better isolate defective aspects of the cells.
Accordingly, objects of the present invention are to provide a circuit and method for isolating test voltages for improved functional testing of SRAM devices.